The present invention relates to a multi-chip package with a LOC lead frame, in particular about the type of multi-chip package with thick tapes sticking to the LOC lead frame.
In the past, a common making process of semiconductor devices use a lead frame to support and electrically connect to a semiconductor chip, and then seals the chip with a package body. To achieve higher performance and larger memory capacity, the semiconductor chip has become smaller and more accurate. An idea of stacking and sealing a number of semiconductor chips in the package body during packaging process has also been proposed. A manufacturing process of a multi-chip package has been claimed in the U.S. Pat. No. 5,366,933. As shown in FIG. 1, the multi-chip package 10 is used. to seal the bottom chip 11 and the upper chip 12, wherein it comprises a bottom chip 11, an upper chip 12, a lead frame, a plurality of bonding wires 16 and 17, and a package body 18. This general type of lead frame comprises a plurality of leads 13 and a dice pad 14. Adhesive films 15 are applied to stick the bottom chip 11 and the upper chip 12 respectively to the bottom and the upper surface of the dice pad 14. A plurality of bonding wires 16 are further used to connect the bottom chip 11 and the leads 13 by wire-bonding technique, while a plurality of bonding wires 17 are used to connect the upper chip 12 and the leads 13 by wire-bonding technique as well. Because the bottom chip 11 and the upper chip 12 are adhesively stuck to the dice pad 14 with their back surface, an overturn action of the dual chip assembly is necessary during the wire-bonding process. To avoid compressing or scratching the bonding wires 16 during the second wire-bonding process, the manufacture processes of this multi-chip package 10 are in the order of sticking the bottom chip 11, forming bonding wires 16 to connect the bottom chip 11 and the lead frame, first time of molding and curing. (the bottom part of the package body 18), sticking the upper chip 12, forming bonding wires 17 to connect the upper chip 12 and the lead frame, second time of molding and curing (the upper part of the package body 18). Nevertheless, such processes are not widely accepted under taking manufacturing efficiency and cost of molds development into consideration.
Another type of multi-chip package is claimed in the U.S. Pat. No. 6,118,176. A LOC lead frame is used to support the upper chip and the bottom chip. The so-called LOC lead frame is the type of lead-on-chip lead frame for short. That is, the leads of the lead frame are extended on the chip for electrical connection and support of the chip without using the dice pad of the lead frame. Such a multi-chip package comprises a dual chip assembly with back-to-back sticking configuration, while the leads of the LOC lead frame are extend on the bottom surface of the bottom chip and fixed with an adhesive film. A circuit board is sticking.:on the upper surface of the upper chip, so as to enable the bonding wires to electrically connect the upper chip and the circuit board, as well as the circuit board and the leads. Likewise, the manufacture of such a multi-chip package must also involve an overturn action for wire bonding, the bonding wires on the bottom chip, however may be scratched during the wire-bonding process of the upper chip.
The major object of the present invention: is to provide a multi-chip package, which uses a LOC lead frame and a plurality of tapes to integrate a plurality of vertically stacked chips. With the thickness of the corresponding tape underneath the chip, such a package can avoid compressing the bonding wires beneath the chip, therefore no overturn action is necessary while packaging the upper and bottom chips.
In accordance with the multi-chip package of the present invention, it mainly comprises a LOC lead frame, the first chip, the second chip and a package body. Such a LOC lead frame possesses a plurality of leads, and can be from inside to outside divided into the first inner portion, the second inner portion and the outer connecting portion, where the first inner portion forms a downset. The first chip is located beneath the first inner portion of the plurality of leads, and its top surface is sticking to the first inner portion of the leads in the LOC lead frame by the first tape. The top surface of the first chip possesses a plurality of chip pads to enable a plurality of the first bonding wire to electrically connect the chip pads of the first chip and the first inner portion. of the corresponding leads. The second chip is located above the plurality of leads of the first inner portion, and its bottom surface is sticking to the first inner portion of the leads in the lead frame by the second tape. The thickness of the second tape can avoid the first bonding wire contacting the bottom surface of the second chip. The top surface of the second chip possesses a plurality of chip pads to enable the plurality of bonding wires to electrically connect the chip pads of the second chip and the second inner portion of the corresponding leads. The package body packages the first chip, the second chip, the boding wires, and the first and the second inner portion of the lead frame.